Main Points:
- This paper is another important step in the emergence of software-based routers. The authors describe their experiences using network processors like Intel IXP1200 to build a router.
- They propose a processor hierarchy in the routers, by having the data plane (data packets) handled by a microengine at line speeds, whereas the control plane traffic (control packets like LDP, route calculation etc) handled by sophisticated Pentium at the top of the hierarchy. This ensures separation of functionalities and responsibilities across layers.
- The paper provides immense insight to a network designer into the general approach to design a network router. They describe the hardware used, the data structures involved at the classifier, forwarder and scheduler, and the queuing discipline they employed.
Problems:
While they dwell on the possibility of having multiple forwarders between classifier and scheduler, they do not adequately consider such scenarios in their implementation. They mention that to simplify their analysis, they have considered only the straight-forward input-port/output-port forwarding.
Future Work:
I see scope for future work in the aspect of using different hardware. They use 700 Mhz processor at the lowest level. If today’s technology permits them to use a much more sophisticated processor there, would there be a possibility of shifting some of the control traffic handling to the lower layer — thereby, avoiding some of the performance loss due to layering.